SRAM cell arrangement and method for manufacturing same

ABSTRACT

An SRAM cell arrangement which includes six MOS transistors per memory cell wherein each transistor is formed as a vertical transistors. The MOS transistors are arranged at sidewalls of trenches. Parts of the memory cell such as, for example, gate electrodes or conductive structures fashioned as spacers are contacted via adjacent, horizontal, conductive structures arranged above a surface of a substrate. Connections between parts of memory cells occur via third conductive structures arranged at the sidewalls of the depressions and word lines via diffusion regions that are adjacent to the sidewalls of the depressions within the substrate, via first bit lines, via second bit lines and/or via conductive structures that are partially arranged at different heights with respect to an axis perpendicular to the surface. Contacts contact a plurality of parts of the MOS transistors simultaneously.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates, generally, to an SRAM cell arrangement having a plurality of memory cells and, more specifically, to such an SRAM cell arrangement wherein each of its memory cells respectively includes 6 vertical MOS transistors such that various contacts contact a plurality of parts of the transistors simultaneously.

2. Description of the Prior Art

An SRAM cell arrangement is a memory cell arrangement with random access to stored information. In contrast to a DRAM cell arrangement wherein the information must be refreshed at regular time intervals, the information is statically stored in an SRAM sell arrangement.

What are referred to as 6T memory cells are being increasingly utilized in SRAM cell arrangements. A 6T memory cell includes four MOS transistors interconnected as a flipflop and two selection transistors. The flipflop is one of the two stable conditions. The condition of the flipflop represents a logical quantity, 0 or 1. By driving the selection transistors via a word line, the condition can be determined via two bit lines. Thus, the information can be read out and the condition can be modified and, thus, new information can be stored.

Since the memory density is increasing from memory generation to memory generation, the required area of the 6T memory cell must be reduced from generation to generation. Semiconductor International (November 1996) pages 19 and 20, presents a 6T memory cell that can be manufactured with an area of 55F², whereby F is the minimum structural size that can be manufactured in the respective technology. Self-aligned contacts (i.e., contacts without utilization of aligning masks), are produced and local connections (i.e., connections that lie within the cell, are utilized.

The present invention is based on the problem of specifying an SRAM cell arrangement that includes 6T memory cells as memory cells and can be manufactured with especially high packing density. Further, a manufacturing method for such an SRAM cell arrangement should be specified.

SUMMARY OF THE INVENTION

Such problem is addressed by the present invention in an SRAM call arrangement having a plurality of memory cells wherein each memory cell includes 6 vertical MOS transistors with connections between parts of the transistors being as follows. A first source/drain region of a first transistor is connected to a first source/drain region of a second transistor and to a first voltage terminal. A second source/drain region of the first transistor is connected to a first source/drain region of a third transistor, a first source/drain region of a fifth transistor, a gate electrode of the second transistor and a gate electrode of a fourth transistor. A gate electrode of the first transistor is connected to a second source/drain region of the second transistor, a first source/drain region of the fourth transistor, a gate electrode of the third transistor and a first source/drain region of a sixth transistor. A second source/drain region of the third transistor is connected to a second source/drain region of the fourth transistor and a second voltage terminal. A second source/drain region of the fifth transistor is connected to a first bit line. A gate electrode of the fifth transistor is connected to a gate electrode of the sixth transistor and to a word line. A second source/drain region of the sixth transistor is connected to a second bit line. The third transistor and the fourth transistor are complementary to the first transistor, the second transistor, the fifth transistor and the sixth transistor. It lies within the scope of the present invention for improving various properties of the memory cell for the SRAM cell arrangement to integrate further complements such as, for example, capacitors, into the memory cell in addition to the sixth transistors of a memory cell.

In the inventive SRAM cell arrangement, the sixth transistors of each memory cell are formed as vertical transistors. The area of the memory cell thereby becomes particularly small.

The six transistors are formed at sidewalls of stripe-shaped depressions proceeding parallel to one another, which can be formed as trenches in a substrate, as a result whereof the density of the connections is increased and the area of the memory cell is reduced. The first transistor and the second transistor are arranged at a second sidewall of a first trench; the fifth transistor and the sixth transistor are to be arranged at a second sidewall of a second trench; and the third transistor and the fourth transistor are arranged of a first sidewall of the fourth trench. Third trenches filled with insulating material can, as insulating structures, insulate parts of transistors, which are complementary with one another, from one another.

It is advantageous to respectively formed gate electrodes of the six transistors as a spacer that adjoins a horizontal conductive structure arranged outside the depressions. The structure that is formed from the spacer and the horizontal, conductive structure is also referred to as strap. It enables a separate connection of the gate electrodes via an appertaining, horizontal, conductive structure to other parts of the transistors. For producing the horizontal, conductive structure before the production of the trenches, it is advantageous to generate a conductive layer. As a result, the spacer is connected in self-aligned fashion to the horizontal, conductive structure that arises from the conductive layer.

For diminishing the plurality of contacts and, thus, the area of the memory cell, it is advantageous to arrange contacts such that they partially overlap laterally with the horizontal, include conductive structures.

For increasing the density of the connections and, thus, for reducing the area of the memory cell, it is advantageous to employ a plurality of connection planes that conductive structures, bit lines and/or word lines.

So that no current flows along the sidewalls of the depressions between neighboring source/drain regions of different transistors, highly doped channel stop regions can be generated between the transistors by oblique implantation at the sidewalls of the depressions. The channel stop regions are doped with a conductivity type that is opposite the conductivity type of the neighboring source/drain regions.

For connecting neighboring source/drain regions that are located at a different height relative to an axis that proceeds perpendicular to a surface of the substrate, it is advantageous to generate highly doped diffusion regions. The diffusion regions can be generated by oblique implantation at parts of the sidewalls of the depressions. The diffusion regions are doped with the conductivity type of the neighboring source/drain regions.

When source/drain regions are generated after generating the depressions by implantation, then it is advantageous to provide the sidewalls of the depressions with spacers and to provide parts of the memory cell with a preliminary structure before the implantation in order to protect the sidewalls and the parts of the memory cell from the implantation.

It is advantageous to formed the word line as a spacer along a sidewall of one of the depressions. The first bit line and the second bit line are formed transversely relative to the word line.

For reducing the area of the memory cell, it is advantageous when the fifth gate electrode of the fifth transistor and the sixth gate electrode of the sixth transistor are parts of the word line.

It is further advantageous to arrange memory cells neighboring along the first bit line mirror-symmetrically relative to an axis that proceeds along a center line of a depression, namely such that the depression is divided by the memory cells. The area of a memory cell is diminished as a result thereof.

It is advantageous to form transistors complementary to one another at different depressions. As a result, floors of the depressions can be continuously doped by respectively one conductivity type and can be simultaneously employed as source/drain regions and as conductive structures.

It is advantageous to arrange a first insulating structure that, for example, can be formed as a depression filled with insulating material between a depression at which transistors are formed and a neighboring transmission at which complementary transistors are formed.

It is advantageous to form a first conductive structure or, respectively, a second conductive structure that is connected to a first voltage terminal or, to a second voltage terminal respectively along a floor of a depression in the form of a doped region within the substrate. For reducing the area of the memory cell, it is advantageous when the first source/drain region of the first transistor and the first source/drain region of the second transistor are parts of the second conductive structure, and the second source/drain region of the third transistor and the second source/drain region of the fourth transistor are parts of the first conductive structure.

For increasing the density of the connections, it is advantageous to employ conductive structures arranged in an additional connecting level, these being arranged in the form of spacers at sidewalls of depressions and connecting parts of transistors.

Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and the Drawings.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a portion from a surface of a substrate which includes a memory cell. The surface is divided into horizontal regions and vertical regions which overlap the horizontal regions;

FIG. 2 shows a cross-section along a boundary line of a seventh horizontal region and an eighth horizontal region through the substrate after first insulating structures, first doped wells, second doped wells, first source/drain regions of fourth transistors, second source/drain regions of second transistors, second source/drain regions of first transistors, first source/drain regions of third transistors, second source/drain regions of fifth transistors and second source/drain regions of sixth transistors were produced;

FIG. 3 shows the cross-section from FIG. 2 after a second insulating structure, a conductive layer, a preliminary structure, first trenches, second trenches, fourth trenches, channel stop regions, diffusion regions, spacers, first conductive structures, first source/drain regions of the first transistors, first source/drain region of the second transistors, first source/drain regions of the fifth transistor, first source/regions of the sixth transistors, second conductive structures, second source/drain regions of the third transistors and second source/drain regions of the fourth transistors were produced;

FIG. 4 shows the cross-section from FIG. 3 after a gate dielectric, gate electrodes, third conductive structures and horizontal, conductive structures were produced;

FIG. 5 shows the cross-section from FIG. 4 after second contacts, fourth contacts, fifth contacts, sixth contacts, fifth conductive structures, sixth conductive structures and a third insulating structure were produced;

FIG. 6a shows the cross-section from FIG. 5 after a fourth insulating structure, first contacts, third contacts, seventh contacts, eighth contacts, fourth conductive structures, first bit lines and second bit lines were produced;

FIG. 6b shows the substrate from FIGS. 6a in a cross-section parallel to the cross-section of FIG. 6a along the one boundary line between a thirteenth horizontal region and a fourteenth horizontal region;

FIG. 6c shows the substrate of FIG. 6a in a cross-section parallel to the cross-section of FIGS. 6a along a twelfth horizontal region;

FIG. 6d shows a cross-section perpendicular to the cross-section of FIG. 6a through the substrate of FIG. 6a along a third vertical region;

FIG. 7a shows the portion from FIG. 1 after the first insulating structures in the form of third trenches filled with insulating material were produced, whereupon a fourth mask was applied onto the surface;

FIG. 7b shows the portion from FIG. 7a after the first trenches, the second trenches and the fourth trenches were produced with the assistance of a sixth mask;

FIG. 7c shows the portion from FIG. 7b, whereupon a seventh mask was applied onto the surface;

FIG. 7d shows the portion from FIG. 7c, whereupon an eighth mask was applied onto the surface;

FIG. 7e shows the portion from FIG. 7d, whereupon an eleventh mask was applied onto the surface;

FIG. 7f shows the portion from FIG. 7e, whereupon a thirteenth mask was applied onto the surface;

FIG. 7g shows the portion from FIG. 7f, whereupon a fourteenth mask was applied onto the surface;

FIG. 7h shows the portion from FIG. 7g, whereupon a sixteenth mask was applied onto the surface;

FIG. 7i shows the portion from FIG. 7a, whereupon a eighteenth mask was applied onto the surface.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, a formulation “region a up to including region β” refers to all regions that are arranged within a memory cell between the region a and the region β as well as the region a and the region β. α and β respectively stand for a number or a letter.

In a first exemplary embodiment, a substrate S is a wafer of silicon. An x-axis x and a y-axis y perpendicular to the x-axis x proceed in a surface O of the substrate S (see FIG. 1). Parts of the surface O at which a respective memory cell is generated are respectively divided into stripe-shaped, horizontal regions adjoining one another and proceeding parallel to the x-axis x. The parts of the surface O are likewise divided into respective stripe-shaped, vertical regions joining one another and proceeding parallel to the y-axis (see FIG. 1). Memory cells which are adjacent, or neighboring, in the direction of the x-axis are generated mirror-symmetrically relative with one another with respect to axes proceeding parallel to the y-axis; either first vertical regions 1 or thirteenth vertical regions 13 of these memory cells adjoining one another. Of respectively two neighboring memory cells to be generated in the direction of the y-axis, a first horizontal region a of one of the memory cells and a twenty second horizontal region v of another adjoin one another.

With the assistance of a first mask (not shown) of photoresist which does not respectively cover the tenth vertical region 10 and the eleventh vertical region 11 in the memory cells, third trenches G3 that are approximately 500 nm deep are generated by etching silicon. The etchant is, for example, HBr+NF₃+He+O₂. By depositing SiO₂ in a thickness of approximately 600 nm in a TEOS process and subsequent re-etching, the third trenches G3 are filled with SiO₂. First insulating structures I1 thereby arise (see FIG. 2).

The first insulating structures I1 are suitable for insulating parts of transistors complementary to one another that are to be produced from one another.

With the assistance of a second mask (not shown) of photoresist, which respectively covers the eleventh vertical region 11 through the thirteenth vertical region 13 in the memory cells, approximately 2 μm deep p-doped, first wells Wa1 are produced by implantation (see FIG. 2).

With the assistance of a third mask (not shown) of photoresist, that respectively does not cover the eleventh vertical region 11 through the thirteenth vertical region 13 in the memory cells, approximately 2 μm deep n-doped second wells Wa2 are generated by implantation (see FIG. 2). The first insulating structures I1, thus, respectively proceed between a first well Wa1 and a second well Wa2. The first well Wa1 and the second well Wa2 are striped-shaped and proceed substantially parallel to one another. The dopant concentrations of the first wells Wa1 and of the second wells Wa2 amount to approximately 3*10¹⁷ cm⁻³.

With the assistance of a fourth mask M4 of photoresist (see FIG. 7a), hook-shaped, n-doped regions approximately 150 nm deep are generated by implantation within the first well Wa1. The dopant concentration of the hook-shaped regions amounts to approximately 5*10²⁰ cm⁻³. Parts of the hook-shaped regions are suitable as second source/drain regions 1 S/D1 of first transistors, as second source/drain regions 2 S/D1 of second transistors, as second source/drain regions 5 /SD2 of fifth transistors and as second source/drain regions 6 S/D2 of sixth transistors (see FIG. 2).

To that end, the fourth mask M4 respectively does not cover regions in the memory cells: wherein the fourteenth horizontal region n through the twenty-first horizontal region u overlap with the first vertical region 1 through the fifth vertical region 5; wherein the fourth horizontal region d through the tenth horizontal region j overlap with the first vertical region 1 through the fifth vertical region 5; wherein the fourteerth horizontal region n up to including the seventeenth horizontal region q overlap with the sixth vertical region 6 and the seventh vertical region 7; wherein the fourth horizontal region d through the seventh horizontal region g overlap with the sixth vertical region 6 and the seventh vertical region 7; wherein the eleventh horizontal region k through the seventeenth horizontal region q overlap with the eighth vertical region 8 and the ninth vertical region 9; and wherein the first horizontal region a through the seventh horizontal region g overlap with the eighth vertical region 8 and the ninth vertical region 9.

With the assistance of a fifth mask (not shown) of photoresist, rectangular, p-doped regions approximately 150 nm deep are generated within the second wells Wa2. The dopant concentration of the rectangular regions amounts to approximately 5*10²⁰ cm⁻³. The p-doped regions are suitable as first source/drain regions 3 S/D1 of third transistors and first source/drain regions 4 S/D1 of fourth transistors (see FIG. 2).

To that end, the fifth mask does not cover regions wherein the fourteenth horizontal region n through the twentieth horizontal region t overlap with the eleventh vertical region 11 through the thirteenth vertical region 13, and regions wherein the third horizontal region c through the tenth horizontal region j overlap with the eleventh vertical region 11 through the thirteenth vertical region 13. Subsequently, a first insulating layer (not shown) is generated in that SiO₂ is deposited in a thickness of approximately 100 nm. An approximately 100 nm thick, conductive layer S1 is generated over the first insulating layer by deposition of doped polysilicon. A second insulating layer (not shown) is generated over the conductive layer S1 in that SiO₁ is deposited in a thickness of a approximately 100 nm (see FIG. 3).

With the assistance of a stripe-shaped, sixth mask M6 of photoresist (see FIG. 7b), approximately 500 nm deep, first trenches G1, second trenches G2 and fourth trenches G4 are produced parallel to the third trenches G3 by etching silicon and SiO₂ (see FIG. 3). The depth of the first trenches G1, of the second trenches G2 and of the fourth trenches G4 starting from the surface O amounts to approximately 500 nm. The first transistor G1 and the second trenches G2 proceed within the first wells Wa1. The fourth trenches G4 proceed within the second wells Wa2. A second insulating structure I2 thereby arises from the first insulating layer, and a preliminary structure VS arises from the second insulating layer.

To that end, the sixth mask M6 respectively does not cover the first vertical region 1, the sixth vertical region 6, the seventh vertical region 7 and the thirteenth vertical region 13 in the memory cells.

With the assistance of a seventh mask M7 of photoresist (see FIG. 7c) and an eighth mask M8 of photoresist (see FIG. 7d), p-doped, first channel stop regions Cl are produced by oblique implantation at second sidewalls 1F2 of the first trenches G1, at first sidewalls 2F1 of the second trenches G2 and at second sidewalls 2F2 of the second trenches G2 (see FIG. 3).

To that end, the seventh mask M7 respectively covers the second well Wa2, as well as regions in the memory cells wherein the eighteenth horizontal region r through the twentieth horizontal region t overlap with the first vertical region 1 through the eighth vertical region 8, and regions wherein the eighth horizontal region h through the tenth horizontal region j overlaps with the first vertical region 1 through the eighth vertical region 8. The eighth mask M8 respectively covers the second well Wa2 in the memory cell, as well as regions: wherein the eighth horizontal region h through the tenth horizontal region j overlaps with the first vertical region 1 and the second vertical region 2; wherein the eighteenth horizontal region r through the twentieth horizontal region t overlap with the first vertical region 1 and the second vertical region 2; wherein the fourteenth horizontal region n through the sixteenth horizontal region p overlaps with the seventh vertical region 7 through the ninth vertical region 9; and wherein the third horizontal region c through the sixth horizontal region f overlap with the seventh vertical region 7 through the ninth vertical region 9.

With the assistance of a ninth mask (not shown) of photoresist, n-doped, second channel stop regions C2 are produced by oblique implantation at first sidewalls 4F1 of the fourth trenches G4 (not visible in the cross-section shown in FIG. 3, but see FIG. 6b).

To that end, the ninth mask in the memory cells respectively covers the first wells Wa1 as well as regions wherein the eighteenth horizontal region r through the twentieth horizontal region t overlap with the twelfth vertical region 12 and the thirteenth vertical region 13, and regions wherein the eighth horizontal region h through the tenth horizontal region j overlap with the twelfth vertical region 12 and the thirteenth vertical region 13.

The first channel stop regions C1 and the second channel stop regions C2 together form channel stop regions C. The dopant concentration of the channel stop regions C amounts to approximately 10¹⁹cm⁻³ and is higher then the dopant concentration of the first wells Wa1 and of the second wells Wa2. As a result of their high dopant concentration, the channel stop regions C prevent a flow of current between neighboring source/drain regions.

With the assistance of a tenth mask (not shown) of photoresist, n-doped diffusion regions are generated by oblique implantation at the first sidewalls 2F1 of the second trenches G2.

To that end, the tenth mask in the memory cells respectively does not cover regions wherein the seventeenth horizontal region q through the twenty-first horizontal region u overlap with the fourth vertical region 4 through the eighth vertical region 8, and regions wherein the seventh horizontal region g through the eleventh horizontal region k overlap with the fourth vertical region 4 through the eighth vertical region 8.

The diffusion regions are divided into first and second diffusion regions D2 (see FIG. 3). The first diffusion regions adjoin the second source/drain regions 1 S/D2 of the first transistors, and the second diffusion regions D2 adjoin the second source/drain regions 2 S/D2 of the second transistors. The dopant concentration of the diffusion regions is high and amounts to approximately 10²⁰ cm⁻³.

Subsequently, SiO₂ is deposited in a thickness of approximately 80 nm in a TEOS process and is etched back in order to generate spaces Sp at the second sidewalls IF2 of the first trenches G1, at the first sidewalls 2F1 of the second trenches G2, at the second sidewalls 2F2 of the second trenches G2, at the first sidewalls 4F1 of the fourth trenches G4 and at the second sidewalls of the fourth trenches G4.

With the assistance of an eleventh mask M11 of photoresist (see FIG. 7e), n-doped, first source/drain regions 5 S/D1 of the fifth transistors (not visible in the cross-section shown in FIG. 3, but see FIG. 6b) and first source/drain regions 6 S/D1 of the sixth transistors are generated by implantation at floors of the second transistors G2 with a respective dopant concentration of approximately 5*10² cm³, and n-doped, first conductive structures L1 are also generated at floors of the first trenches G1 (see FIG. 3). The first conductive structures L1 proceed along the floors of the first trenches G1 and are connected to a first voltage terminal. Parts of the first conductive structures L1 are suitable as first source/drain regions of the first transistors and as first source/drain regions 2 S/D1 of the second transistors (see FIG. 3).

To that end, the eleventh mask M11 in the memory cells respectively does not cover the first trenches G1 nor regions wherein the fourteenth horizontal region n through the twentieth horizontal region t overlap with the third vertical region 3 through the eighth vertical region 8, and rectangular regions wherein the third horizontal region c through the tenth horizontal region j overlap with the third vertical region 3 through the eighth vertical region 8. As a result, the first source/drain regions 5 S/D1 of the fifth transistors are insulated from the first source/drain regions 6 S/D1 of the sixth transistors.

With the assistance of a twelfth mask (not shown) of photoresist, which does not cover the fourth trenches G4 in the memory cells, p-doped, second conductor structures L2 are generated by implantation at the floors of the fourth trenches G4 (see FIG. 3). The dopant concentration of the second conductive structures L2 amounts to approximately 5*10²⁰ cm⁻³. The second conductive structures L2 are connected to a second voltage terminal. Parts of the second conductive structure L2 are suitable as second source/drain regions of the third transistors and as second source/drain regions 4 S/D2 of the fourth transistors.

When producing the first source/drain regions 5 S/D1 of the fifth transistors, the first source/drain regions 6 S/D1 of the sixth transistors, the first conductive structures L1 and the second conductive structures L2, the preliminary structure VS and the spacers Sp prevent the implantation of other parts of the memory cells.

SiO₂ is etched with, for example, HF as etchant. As a result, the preliminary structure VS is removed.

Subsequently, a deep dielectric Gd is generated by thermal oxidation (see FIG. 4). In order to remove parts of the gate dielectric Gd at sidewalls of the conductive layer S1 structured by the generation of the first trenches G1, of second trenches G2 and of the fourth trenches G4, doped polysilicon is deposited in a thickness of approximately 40 nm and is etched back to such an extent that the polysilicon is arranged in the form of spacers under the sidewalls of the structured, conductive layer S1. Subsequently, SiO₂ is etched such with, for example, HF that sidewalls of the structured, conductive layer S1 are uncovered.

Doped polysilicon is deposited in a thickness of approximately 80 nm and is etched back. As a result, spacers that contact the structured, conductive layer S1 arise at the sidewalls of the first trenches G1, of the second trenches G2 and of the fourth trenches G4.

With the assistance of a thirteenth mask M13 of photoresist (see FIG. 7f), silicon is etched such that parts of the spacers are removed. C₂F₆+O₂, for example, is suitable as etchant. As a result, first gate electrodes of the first transistors, second gate electrodes Ga2 of the second transistors, third gate electrodes of the third transistors, fourth gate electrodes Ga4 of the fourth transistors and third conductive structures L3 that are arranged at the first sidewalls 2F1 of the second trenches G2 arise (see FIG. 4). Spacers that are arranged at the second sidewalls 2F2 of the second trenches G2 are not etched and are suitable as word lines W. Parts of the word lines W are suitable as fifth gate electrodes Ga5 of the fifth transistors and as sixth gate electrodes of the sixth transistors.

To that end, the thirteenth mask M13 in the memory cells respectively does not cover regions: wherein the fifteenth horizontal region O through the seventh horizontal region q overlap with the first vertical region 1 and the second vertical region 2; wherein the fifteenth horizontal region O through the seventh horizontal region q overlap with the twelfth vertical region 12 and the thirteenth vertical region 13; wherein the first horizontal region a through the seventh horizontal region g overlap with the first vertical region 1 and the second vertical region 2; wherein the first horizontal region a through the fourth horizontal region d overlap with the third vertical region 3 through the sixth vertical region 6; and wherein the first horizontal region a through the seventh horizontal region g overlap with the twelfth vertical region 12 and the thirteenth vertical region 13.

With the assistance of a fourteenth mask M14 of photoresist (see FIG. 7g), first horizontal, conductive structures H1, second horizontal, conductive structures H2, third horizontal, conductive structures, fourth horizontal, conductive structures H4 and fifth horizontal, conductive structures H5 arise from the structured, conductive layer SI (see FIGS. 4, 6 b, 6 d), C₂F₆+O₂, for example, is suitable as etchant.

To that end, the fourteenth mask M14 covers regions: wherein the eighteenth horizontal region r through the twenty-first horizontal region v overlap with the first vertical region 1 through the sixth vertical region 6; wherein the twelfth horizontal region I through the fourteenth horizontal region n overlap with the first vertical region 1 through the fourth vertical region 4; wherein the eighteenth horizontal region through the twenty-first horizontal region v overlap with the eleventh vertical region 11 through the thirteenth vertical region 13; wherein the twelfth horizontal region I through the fourteenth horizontal region n overlap with the eleventh vertical region 11 through the thirteenth vertical region 13; and wherein the fifth horizontal region e through the eighth horizontal region h overlap with the fourth vertical region 4 through the sixth vertical region 6. The first horizontal, conductive structures H1 adjoin the first gate electrodes Gal of the third transistors at the third conductive structures L3. The second horizontal conductive structures H2 adjoin the second gate electrodes Ga2 of the second transistors. The third horizontal conductive structures adjoin the third gate electrode Ga3 of the third transistors. The fourth horizontal conductive structures H4 adjoin the fourth gate electrodes Ga4 of the fourth transistors. The fifth horizontal conductive structures H5 adjoin the third conductive structures L3.

Subsequently, SiO₂ is deposited in a thickness of approximately 600 nm in a TEOS process. By chemical-mechanical polishing, 500 nm SiO₂ is eroded and planarized, wherein a third insulating structure 13 arising (see FIG. 5).

After generation of second contacts K2 that contact the second source/drain regions 1 S/D2 of the first transistors, of fourth contacts that contact the first source/drain regions 3 S/D1 of the third transistors, of fifth contacts K2 that contact the second source/drain regions 2 S/D2 of the second transistors and of sixth contacts that contact the first source/drain regions 4 S/D1 of the fourth transistors, SiO₂ is selectively etched relative to silicon with the assistance of a fifteenth mask (not shown) of photoresist until parts of the source/drain regions are uncovered. CHF₃+O₂, for example, is suitable as etchant.

To that end, the fifteenth mask in the memory cells respectively does not cover regions: wherein the thirteenth horizontal region M through the fifteenth horizontal region 0 overlap with the second vertical region 2 through the fourth vertical region 4; wherein the fifth horizontal region e through the eighth horizontal region h overlap the third vertical region 3 through the fifth vertical region 5; wherein the thirteenth horizontal region m through the fifteenth horizontal region O overlap with the twelfth vertical region 12; and wherein the third horizontal region c through the sixth horizontal region f overlap with the twelfth vertical region 12.

Subsequently, tungsten is deposited in a thickness of approximately 200 nm. As a result, the second contacts K2, the fourth contacts K4, the fifth contacts K5 and the sixth contacts arise (see FIGS. 5, 6 b). Tungsten is etched with the assistance of a sixteenth mask M16 of photoresist (see FIG. 7h). As a result whereof, fifth conductive structures L5 and sixth conductive structures L6 arise (see FIGS. 5, 6 b). SF₆, for example, is suitable as etchant. The fifth conductive structures L5 respectively adjoin a second contact K2 and a fourth contact K4. The sixth conductive structures L6 respectively adjoin a fifth contact K5 and a'sixth contact.

To that end, the sixteenth mask M16 in the memory cells respectively covers a first U-shaped region and a second U-shaped region. The first U25 shaped region is composed of regions: wherein the thirteenth horizontal region m through the seventeenth horizontal region q overlap with the second vertical region 2 through the fourth vertical region 4; wherein the fifteenth horizontal region o through the seventeenth horizontal region q overlap with the fifth vertical region 5 through the eleventh vertical region 11; and wherein the thirteenth horizontal region m up through the seventeenth horizontal region q overlap with the twelfth vertical region 12. The second U-shaped region is composed of regions: wherein the fourth horizontal d through the ninth horizontal region i overlap with the third vertical region 3 through the fifth vertical region 5; wherein the seventh horizontal region g through the ninth horizontal region i overlap with the sixth vertical region 6 through the eleventh vertical region 11; and wherein the third horizontal region c through the ninth horizontal region i overlap with the twelfth vertical region 12.

Borophosphorous glass is deposited in a thickness of approximately 600 nm. The borophosphorous glass is planarized with the assistance of chemical-mechanical polishing. As a result, a fourth insulating structure 14 arises (see FIG. 6a). For producing first contacts K1 that contact the second source/drain regions 1 S/D2 of the first transistors, for producing third contacts that contact the first source/drain regions 3 S/D1 of the third transistors for producing seventh contacts K7 that contact the second source/drain regions 5 S/D2 of the fifth transistors, and for producing eighth contacts that contact the second source/drain regions 6 S/D2 of the sixth transistors, borophosphorous glass is etched selectively relative to silicon with the assistance of a seventeenth mask (not shown) of photoresist until parts of the source/drain regions are uncovered. C₂F₆+O₂, for example, is suitable as etchant.

To that end, the seventeenth mask in the memory cells respectively does not cover regions: wherein the nineteenth horizontal region s through the twenty-first horizontal region u overlap with the second vertical region 2 through the fourth vertical region 4; wherein the nineteenth horizontal region s through the twenty-first horizontal region u overlap with the twelfth vertical region 12; wherein the eleventh horizontal region k through the thirteenth horizontal region m overlap with the ninth vertical region 9; and wherein the second horizontal region b through the fifth horizontal region e overlap with the ninth vertical region 9. Subsequently, tungsten is deposited in a thickness of approximately 300 nm and is etched back. As a result, the first contacts K1, the third contacts, the seventh contacts K7 and the eighth contacts arise (see FIGS. 6b, 6 d).

Subsequently, AlSiCu is deposited in a thickness of approximately 500 nm and is structured with an eighteenth mask M18 of photoresist (see FIG. 7i) on the basis of an etching step. BCl₃+Cl₂+N₂+CH₄, for example, is suitable as etchant. As a result thereof, fourth conductor structures L4, first bit lines B1 and second bit lines B2 (see FIGS. 6a, 6 b, 6 d) arise. In a memory cell, a fourth conductor structure L4 adjoins a first contact K1 and a third contact. The first bit lines B1 are stripe-shaped and proceed perpendicularly to the first trenches G1 and adjoin the seventh contacts K7. The second bit lines B2 are substantially stripe-shaped and proceed parallel to the first bit lines B1 and adjoin the eighth contacts.

To that end, the eighteenth mask M18 in the memory cells respectively cover regions: wherein the seventeenth horizontal region q through the twenty-first horizontal region u overlap with the second vertical region 2 through the fourth vertical region 4, and regions wherein the seventeenth horizontal q through the nineteenth horizontal region s overlap with the fifth vertical region 5 through the eleventh vertical region 11; and wherein the seventeenth horizontal region q through the twenty-first horizontal region u overlap with the twelfth region 12; the eleventh horizontal region k, the twelfth horizontal region 1, the thirteenth horizontal region m, the fourth horizontal region d, the fifth horizontal region e, the sixth horizontal region f, the seventh horizontal region g and regions wherein the second horizontal region b and the third horizontal region c overlap with the nineteenth vertical region 9.

Many modifications of the exemplary embodiment are conceivable which still would lie within the scope of the present invention. In particular, the dimensions of the described layers, regions, areas and trenches can be adapted to the respective requirements. The same is also true of the proposed dopant concentrations. Structures and layers of SiO₂ can, in particular, be produced by thermal oxidation or by a deposition process. Polysilicon can be doped both during as well as following the deposition. Instead of doped polysilicon, metal silicides and/or metals, for example, can be employed. Instead of eroding deposited SiO₂ by chemical-mechanical polishing, re-etching also can be employed. The same considerations are also true for the generation of the conductive structure.

In sum, although the present invention has been described with reference to specific embodiments, those of skill in the art will recognize that changes may be made thereto without departing from the spirit and scope of the invention as set forth in the hereafter appended claims. 

What is claimed is:
 1. An SRAM cell arrangement comprising a plurality of memory cells, wherein each memory cell respectively comprises: a substrate, a first vertical MOS transistor, a second vertical MOS transistor, a third vertical MOS transistor, a fourth vertical MOS transistor, a fifth vertical MOS transistor, a sixth vertical MOS transistor, a word line, a first bit line, a second bit line, a first conductive structure and a second conductive structure; and wherein the third and fourth transistors are complementary to the first, second, fifth and sixth transistors; wherein a first source/drain region of the first transistor is connected to both a first source/drain region of the second transistor and a first voltage terminal; wherein a second source/drain region of the first transistor is connected to each of a first source/drain region of the third transistor, a first source/drain region of the fifth transistor, a gate electrode of the second transistor and a gate electrode of the fourth transistor; wherein a gate electrode of the first transistor is connected to each of a second source/drain region of the second transistor, a first source/drain region of the fourth transistor, a gate electrode of the third transistor and a first source/drain region of the sixth transistor; wherein a second source/drain region of the third transistor is connected to both a second source/drain region of the fourth transistor and a second voltage terminal; wherein a second source/drain region of the fifth transistor is connected to the first bit line; wherein a gate electrode of the fifth transistor is connected to both a gate electrode of the sixth transistor and the word line; wherein a second source/drain region of the sixth transistor is connected to the second bit line; wherein the first and second transistors are arranged at a second side wall of a first trench formed in the substrate; wherein the fifth and sixth transistors are arranged at a second side wall of a second trench formed in the substrate which is parallel to the first trench; wherein the third and fourth transistors are arranged at a first side wall of a fourth trench formed in the substrate which is parallel to the second trench; wherein the word line is arranged along the second side wall of the second trench; wherein the first conductive structure is connected to the first voltage terminal; wherein the second conductive structure is connected to the second voltage terminal; wherein the first conductive structure is arranged along the first trench; wherein the second conductive structure is arranged along the fourth trench; wherein the first bit line and the second bit line are both arranged transversely relative to the word line and are arranged parallel to one another; wherein the first source/drain region of the first transistor and the first source/drain region of the second transistor are both connected to the first conductive structure; and wherein the second source/drain region of the third transistor and the second source/drain region of the fourth transistor are both connected to the second conductive structure.
 2. An SRAM cell arrangement as claimed in claim 1, wherein at least one of the gate electrodes and the conductive structures are adjacent to horizontal conductive structures arranged outside the first, second and fourth trenches above a surface of the substrate via which they are contacted.
 3. An SRAM cell arrangement as claimed in claim 2, wherein each memory cell further respectively comprises a third conductive structure, a fourth conductive structure, a fifth conductive structure, a sixth conductive structure, a first horizontal conductive structure, a second horizontal conductive structure, a third horizontal conductive structure, a fourth horizontal conductive structure, a fifth horizontal conductive structure, a second insulating structure, a first diffusion region and a second diffusion region; and wherein the first trench and the second trench are arranged in a first well of the substrate doped with a second conductivity type; wherein the fourth trench is arranged in a second well of the substrate doped with a first conductivity type which is opposite the second conductivity type; wherein the first conductive structure is adjacent a floor of the first trench within the substrate and is doped with the first conductivity type; wherein the second conductive structure is adjacent a floor of the fourth trench within the substrate and is doped with the second conductivity type; wherein both the first source/drain region of the first transistor and the first source/drain region of the second transistor are parts of the first conductive structure; wherein both the second source/drain region of the third transistor and the second source/drain region of the fourth transistor are parts of the second conductive structure; wherein parts of the second insulating structure are arranged between the first, second, fourth and fifth horizontal conductive structures and the surface of the substrate; wherein the gate electrodes of each of the first, second, third, fourth, fifth and sixth transistors are formed as spacers; wherein the gate electrode of the first transistor adjoins the first horizontal conductive structure; wherein the gate electrode of the second transistor adjoins the second horizontal conductive structure; wherein the gate electrode of the third transistor adjoins the third horizontal conductive structure; wherein the gate electrode of the fourth transistor adjoins the fourth horizontal conductive structure; wherein the word line is formed as a spacer at the second side wall of the second trench; wherein both the gate electrode of the fifth transistor and the gate electrode of the sixth transistor are parts of the word line; wherein the third conductive structure is formed as a spacer at the first side wall of the second trench; wherein the third conductive structure adjoins both the first horizontal conductive structure and the fifth horizontal conductive structure; wherein each of the second side wall of the first trench, the first side wall of the second trench, the second side wall of the second trench and the first side wall of the fourth trench are provided with a gate dielectric; wherein the second source/drain region of the first transistor and the second source/drain region of the second transistor are adjacent each of the surface of the substrate, the second side wall of the first trench and the first side wall of the second trench; wherein the first source/drain region of the third transistor and the first source/drain region of the fourth transistor are adjacent both the surface of the substrate and the first side wall of the fourth trench; wherein the second source/drain region of the fifth transistor and the second source/drain region of the sixth transistor are adjacent both the surface of the substrate and the second side wall of the second trench; wherein the first horizontal conductive structure is connected to the fourth conductive structure via a first contact; wherein the third horizontal conductive structure is connected to the fourth conductive structure via a third contact; wherein the fourth conductive structure is arranged above the second horizontal conductive structure; wherein the second source/drain region of the first transistor is connected to both the second horizontal conductive structure and the fifth conductive structure via a second contact; wherein the fifth conductive structure is arranged above each of the first, second, fourth and fifth horizontal conductive structures and is arranged under the fourth conductive structure; wherein the first source/drain region of the third transistor is connected to both the fourth horizontal conductive structure and the fifth conductive structure via a fourth contact; wherein the second source/drain region of the second transistor is connected to both the fifth horizontal conductive structure and the sixth conductive structure via a fifth contact; wherein a height of the sixth conductive structure relative to an axis perpendicular to the surface of the substrate corresponds to a height of the fifth conductive structure; wherein the first source/drain region of the fourth transistor is connected to the sixth conductive structure via a sixth contact; wherein the second source/drain region of the fifth transistor is connected to the first bit line via a seventh contact; wherein the second source/drain region of the sixth transistor is connected to the second bit line via an eighth contact; wherein the first diffusion region within the substrate is doped with a first conductivity type and is adjacent each of the first side wall of the second trench, the second source/drain region of the first transistor and the first source/drain region of the fifth transistor; and wherein the second diffusion region within the substrate is doped with the first conductivity type and is adjacent each of the first side wall of the second trench, the second source/drain region of the second transistor and the first source/drain region of the sixth transistor.
 4. An SRAM cell arrangement as claimed in claim 1, wherein each memory cell further respectively comprises highly doped channel stop regions and a stripe-shaped, first insulation structure; and wherein the highly doped channel stop regions are arranged within the substrate at pars of the side walls of the trenches at which no gate electrodes and no diffusion regions are adjacent; and wherein the first insulation structure is arranged parallel to and between the second and fourth trenches.
 5. An SRAM cell arrangement as claimed in claim 1, wherein the memory cells neighboring along the first bit line are arranged mirror-symmetrically relative to one another with respect to an axis that proceeds along a center line of one of a first trench and a fourth trench. 